This application makes reference to and claims all benefits accruing under 35 U.S.C. Section 119 from an application entitled, xe2x80x9cMethod for Fabricating Avalanche Photodiode,xe2x80x9d filed in the Korean Industrial Property Office on Jun. 29, 2000 and there duly assigned Ser. No. 2000-36371.
1. Field of the Invention
The present invention relates generally to a method for fabricating an avalanche photodiode. More particularly, the present invention relates to a method for fabricating an avalanche photodiode utilizing a more simplified process, thereby improving a reproducibility of the avalanche phtotodiode.
2. Description of the Related Art
Recently, an avalanche photodiode (APD) is widely used for application in a high-speed optical communication of over 2.5 Gbps. In order to transmit a large amount of information at a transfer rate of over 2.5 Gbps, many researches are currently being conducted to improve and increase the transfer rate.
However, the efforts to increase the transfer rate of the optical communication system leads to an increase in the transmission noises, thus decreasing the receiving sensitivity of the system. In a long-distance optical communication system, the transmission power of an optical signal is decreased due to a power loss in the optical fiber as the transmission distance gets longer. In this type of optical communication system, a Pin (P/intrinsic/n-type conductive) photodiode is typically used as an optical receiver to receive data at a rate of up to 10 Gbps. Having no internal gain, the Pin photodiode can achieve a receiving sensitivity of below xe2x88x9220 dBm. Here, the xe2x80x9creceiving sensitivityxe2x80x9d refers to the receiver capability of processing an optical signal without error. That is, if an optical signal is transmitted to a remote distance through an optical fiber at an initial power level of 1 mW and received at the destination end at a power level of over 10 xcexcW, the signal is considered received within an acceptable error margin.
In contrast, an avalanche photodiode exhibits a higher receiving sensitivity by virtue of its internal gain. For example, the receiving sensitivity of the avalanche photodiode with an internal gain 10 is higher by xe2x88x9230 dBm when compared to the Pin photodiode under the same prevailing conditions. As a consequence, the optical communication system employing the avalanche photodiode as an optical receiver can transmit the optical signal due to more sensitive receiving capability.
The avalanche photodiode, as described in the preceding paragraph, is illustrated in FIG. 1. As shown in FIG. 1, an avalanche photodiode includes a stacked structure of a lower electrode layer 1, an n-type InP substrate 2, an InP buffer layer 3, an InGaAs absorption layer 4, an n-type InGaAs grading layer 5, an n-type InP current adjusting layer 6, and an InP amplifying layer 7 in succession. In addition, a primary diffusion layer 8a and a secondary diffusion layer 8b are formed at the central of the amplifying layer 7. An FGR (Floating Guard Ring) layer 9 is formed at the edge of the amplifying layer 7. The reference numeral 10 indicates a reflection suppressing layer, and the reference numeral 11 indicates an upper electrode layer.
Normally, the avalanche photodiode has a very high operating voltage applied to its diffusion boundary, i.e., a p-n junction formed between the amplifying layer 7 and the primary and secondary diffusion layers 8a and 8b. In particular, if the diffusion boundary has a curvature shape, the current density per unit area increases. Thus, the device may be subject to a breakdown at a lower voltage when compared with a flat diffusion boundary area. Hence, in order to decrease the current density around the primary diffusion layer 8a, the secondary diffusion layer 8b is formed to have a smaller diffusion depth at the edges than the center area. In addition, the FGR layer 9 can obtain a desired gain without a breakdown by changing the distribution of its internal electric field to decrease the strength of an electric field applied between the primary diffusion layer 8a serving as a light-receiving surface and the absorption layer 4. That is, if the FGR layer 9 is formed away from the secondary diffusion layer 8b, the depletion layer extends to the edges of the secondary diffusion layer 8b according to the operating voltage. Meanwhile, if the depletion layer reaches the FGR layer 9, the current density is decreased. As a result, it is possible to increase the operating voltage, thus making it possible to obtain a high internal gain.
Conventionally, in order to manufacture such an avalanche photodiode as described above, the central part of the amplifying layer 7 is etched to a predetermined depth, then the primary diffusion layer 8a is formed in the etched area by a primary diffusion process. Next, the secondary diffusion layer 8b and the FGR layer 9 are formed around the primary diffusion layer 8a by a secondary diffusion process. However, this conventional fabrication method requires the diffusion process to perform several times, thereby increasing the fabrication complexity. Furthermore, the primary diffusion layer 8a formed in the primary diffusion process is diffused again due to the heat applied from the secondary diffusion process, thus making it difficult to accurately control the diffusion depth of the primary diffusion layer 8a. As a consequence, it is not possible to guarantee the reproducibility of the same photodiode.
In the preferred embodiment, the present invention provides an avalanche photodiode fabricating method that is simpler and enables reproducibility of the photodiode.
According to a preferred embodiment, a method of fabricating an avalanche photodiode is provided and includes the steps of: (a) sequentially stacking, in succesion, on an n-type InP substrate, an InP buffer layer, an InGaAs absorption layer, an n-type InGaAsP grading layer, an n-type InP current adjusting layer, and an InP amplifying layer; (b) forming a protection layer on the InP amplifying layer, etching a light-receiving area of the protection layer and the InP amplifying layer to a predetermined depth, and partially etching the protection layer to expose a FGR forming area of the InP amplifying layer; (c) diffusing a diffusion source in the etched light-receiving area and the exposed FGR forming area; (d) forming a reflection suppressing layer on the diffusion layer formed on the light-receiving area by diffusing the diffusion source, the FGR layer and the exposed amplifying layer; (e) forming an upper electrode layer to a predetermined depth from the reflection suppressing layer to the diffusion layer formed on the light-receiving area; and (f) forming a lower electrode layer on a back of the substrate.
The step (b) comprises the steps of primarily etching the light-receiving area of the protection layer and the InP amplifying layer to a predetermined depth by dry etching; and, secondarily etching a boundary etched in the primary etching process by wet etching to relieve a curvature of the etched boundary.
The step (c) comprises the steps of forming the diffusion source layer on the etched light-receiving area and the exposed FGR forming area; forming a diffusion suppressing layer on the diffusion source layer; diffusing the diffusion source into the amplifying layer at a predetermined temperature; and, removing the diffusion suppressing layer.
Preferably, the diffusion source comprises Zn3, and the diffusion suppressing layer is a SiO2 layer.